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R1EX25008ASA00I/r1ex25008ata00i r1ex25016asa00i/r1ex25016ata00i serial peripheral interface 8k eeprom (1024-word 8-bit) 16k eeprom (2048-word 8-bit) electrically erasable and progr ammable read only memory rej03c0396-0100 rev.1.00 nov.24.2009 description r1ex25xxx series is the serial peripheral interface co mpatible (spi) eeprom (electrically erasable and programmable rom). it realizes high speed, low power consumption and a high level of reliability by employing advanced monos memory technology and cmos process and low voltage circuitry technology. it als o has a 32-byte page programming function to make it?s write operation faster. features ? single supply: 1.8 v to 5.5 v ? serial peripheral interface compatible (spi bus) ? spi mode 0 (0,0), 3 (1,1) ? clock frequency: 5 mhz (2.5 v to 5.5 v), 3 mhz (1.8 v to 5.5 v) ? power dissipation: ? standby: 3 a (max) ? active (read): 2.5 ma (max) ? active (write): 3.0 ma (max) ? automatic page write: 32-byte/page ? write cycle time: 5 ms ? endurance: 1,000k cycles @25 c ? data retention: 100 years @25 c ? small size packages: sop-8pin, tssop-8pin ? shipping tape and reel ? tssop-8pin: 3,000 ic/reel ? sop-8pin: 2,500 ic/reel ? temperature range: 40 to + 85 c ? lead free product. rej03c0396-0100 rev.1.00 nov.24.2009 page 1 of 20
r1ex25008axx00i/r1ex25016axx00i ordering information type no. internal organization operating voltage frequen cy package R1EX25008ASA00I 8-kbit (1024 8-bit) 1.8 v to 5.5 v 5 mhz (2.5 v to 5.5 v) r1ex25016asa00i 16-kbit (2048 8-bit) 3 mhz (1.8 v to 5.5v) 150mil 8-pin plastic sop prsp0008df-b (fp-8dbv) lead free r1ex25008ata00i 8-kbit (1024 8-bit) 1.8 v to 5.5 v 5 mhz (2.5 v to 5.5 v) r1ex25016ata00i 16-kbit (2048 8-bit) 3 mhz (1.8 v to 5.5 v) 8-pin plastic tssop ptsp0008jc-b (ttp-8dav) lead free pin arrangement 8-pin sop/tssop (top view) 1 2 3 4 8 7 6 5 v cc hold c d s q w v ss pin description pin name function c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground rej03c0396-0100 rev.1.00 nov.24.2009 page 2 of 20
r1ex25008axx00i/r1ex25016axx00i block diagram high voltage generator memory array y-select & sense amp. serial-parallel converter address generator control logic y decoder x decoder v cc v ss s w c hold d q absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc 0.6 to + 7.0 v input voltage relative to v ss v in 0.5 * 2 to +7.0 * 3 v operating tem perature range * 1 topr 40 to +85 c storage temperature range tstg 55 to +125 c notes: 1. including electrical c haracteristics and data retention. 2. v in (min): 3.0 v for pulse width 50 ns. 3. should not exceed v cc + 1.0 v. dc operating conditions parameter symbol min typ max unit supply voltage v cc 1.8 ? 5.5 v v ss 0 0 0 v input voltage v ih v cc 0.7 ? v cc + 0.5 * 2 v v il 0.3 * 1 ? v cc 0.3 v operating temper ature range topr 40 ? + 85 c notes: 1. v in (min): 1.0 v for pulse width 50 ns. 2. v in (max): v cc + 1.0 v for pulse width 50 ns. capacitance (ta = +25 c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance (d,c, s , w, hold ) cin * 1 ? ? 6.0 pf vin = 0 v output capacitance (q) c i/o * 1 ? ? 8.0 pf vout = 0 v note: 1. not 100 % tested. memory cell characteristics (v cc = 1.8 v to 5.5 v) ta=25 c ta=85 c notes endurance 1,000k cycles min. 100k cycles min. 1 data retention 100 years min. 10 years min. 1 notes: 1. not 100 % tested rej03c0396-0100 rev.1.00 nov.24.2009 page 3 of 20
r1ex25008axx00i/r1ex25016axx00i dc characteristics parameter symbol min max unit test conditions input leakage current i li ? 2 a v cc = 5.5 v, v in = 0 to 5.5 v ( s , d, c, hold , w ) output leakage current i lo ? 2 a v cc = 5.5 v, v out = 0 to 5.5 v (q) v cc current standby i sb ? 3 a v in = v ss or v cc , v cc = 5.5 v active i cc1 ? 2 ma v cc = 3.6 v, read at 5 mhz v in = v cc 0.1/v cc 0.9 q = open ? 2.5 ma v cc = 5.5 v, read at 5 mhz v in = v cc 0.1/v cc 0.9 q = open i cc2 ? 2 ma v cc = 3.6 v, write at 5 mhz v in = v cc 0.1/v cc 0.9 ? 3.0 ma v cc = 5.5 v, write at 5 mhz v in = v cc 0.1/v cc 0.9 output voltage v ol1 ? 0.4 v v cc = 5.5 v, i ol = 2 ma v ol2 ? 0.4 v v cc = 2.5 v, i ol = 1.5 ma v oh1 v cc 0.8 ? v v cc = 5.5 v, i oh = 2 ma v oh2 v cc 0.8 ? v v cc = 2.5 v, i oh = 0.4 ma rej03c0396-0100 rev.1.00 nov.24.2009 page 4 of 20
r1ex25008axx00i/r1ex25016axx00i ac characteristics test conditions ? input pules levels: ? v il = v cc 0.2 ? v ih = v cc 0.8 ? input rise and fall time: 10 ns ? input and output timing reference levels: v cc 0.3, v cc 0.7 ? output reference levels: v cc 0.5 ? output load: 100 pf (ta = 40 to + 85 c, v cc = 2.5 v to 5.5 v) parameter symbol alt min max unit notes clock frequency f c f sck ? 5 mhz s active setup time t slch t css1 90 ? ns s not active setup time t shch t css2 90 ? ns s deselect time t shsl t cs 90 ? ns s active hold time t chsh t csh 90 ? ns s not active hold time t chsl ? 90 ? ns clock high time t ch t clh 90 ? ns 1 clock low time t cl t cll 90 ? ns 1 clock rise time t clch t rc ? 1 s 2 clock fall time t chcl t fc ? 1 s 2 data in setup time t dvch t dsu 20 ? ns data in hold time t chdx t dh 30 ? ns clock low hold time after hold not active t hhch ? 70 ? ns clock low hold time after hold active t hlch ? 40 ? ns clock high setup time before hold active t chhl ? 60 ? ns clock high setup time before hold not active t chhh ? 60 ? ns output disable time t shqz t dis ? 100 ns 2 clock low to output valid t clqv t v ? 70 ns output hold time t clqx t ho 0 ? ns output rise time t qlqh t ro ? 50 ns 2 output fall time t qhql t fo ? 50 ns 2 hold high to output low-z t hhqx t lz ? 50 ns 2 hold low to output high-z t hlqz t hz ? 100 ns 2 write time t w t wc ? 5 ms notes: 1. t ch + t cl 1/f c 2. not 100 % tested. rej03c0396-0100 rev.1.00 nov.24.2009 page 5 of 20
r1ex25008axx00i/r1ex25016axx00i (ta = 40 to + 85 c, v cc = 1.8 v to 5.5 v) parameter symbol alt min max unit notes clock frequency f c f sck ? 3 mhz s active setup time t slch t css1 100 ? ns s not active setup time t shch t css2 100 ? ns s deselect time t shsl t cs 150 ? ns s active hold time t chsh t csh 100 ? ns s not active hold time t chsl ? 100 ? ns clock high time t ch t clh 150 ? ns 1 clock low time t cl t cll 150 ? ns 1 clock rise time t clch t rc ? 1 s 2 clock fall time t chcl t fc ? 1 s 2 data in setup time t dvch t dsu 30 ? ns data in hold time t chdx t dh 50 ? ns clock low hold time after hold not active t hhch ? 140 ? ns clock low hold time after hold active t hlch ? 90 ? ns clock high setup time before hold active t chhl ? 120 ? ns clock high setup time before hold not active t chhh ? 120 ? ns output disable time t shqz t dis ? 200 ns 2 clock low to output valid t clqv t v ? 120 ns output hold time t clqx t ho 0 ? ns output rise time t qlqh t ro ? 100 ns 2 output fall time t qhql t fo ? 100 ns 2 hold high to output low-z t hhqx t lz ? 100 ns 2 hold low to output high-z t hlqz t hz ? 100 ns 2 write time t w t wc ? 5 ms notes: 1. t ch + t cl 1/f c 2. not 100 % tested. rej03c0396-0100 rev.1.00 nov.24.2009 page 6 of 20
r1ex25008axx00i/r1ex25016axx00i timing waveforms serial input timing s c t chsl t slch t chdx t clch t chcl t shch t chsh t shsl t dvch msb in lsb in d q high impedance hold timing t chhl s hold c d q t hlch t chhh t hlqz t hhqx t hhch output timing s c d q lsb out addr lsb in t qlqh t qhql t shqz t ch t cl t clqv t clqx t clqv t clqx rej03c0396-0100 rev.1.00 nov.24.2009 page 7 of 20
r1ex25008axx00i/r1ex25016axx00i pin function serial data output (q) this output signal is used to transfer data serially out of th e device. data is shifted out on the falling edge of serial clock (c). serial data input (d) this input signal is used to transfer data serially into the device. it receives in structions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select ( ) when this input signal is high, the device is deselected and serial data output (q) is at high i mpedance. unless an internal write cycle is in progre ss, the device will be in the standby mode. driving chip select ( s ) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select ( s ) is required prior to the start of any instruction. hold ( ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high im pedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select ( s ) driven low. write protect ( ) the main purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the bp1 and bp0 bits of the status registe r). this pin must be driven either high or low, and must be stable during all write operations. rej03c0396-0100 rev.1.00 nov.24.2009 page 8 of 20
r1ex25008axx00i/r1ex25016axx00i functional description status register the following figure shows the status register format. the status register contains a numbe r of status and control bits that can be read or set (as appropriate) by specific instructions. status register format srwd 0 0 0 bp1 bp0 wel wip b7 status register write disable block protect bits write enable latch bits write in progress bits b0 wip bit: the write in progress (wip) bit indicates whether the memory i s busy with a write or write status register cycle. wel bit: the write enable latch (wel) bit indicates the status o f the internal write enable latch. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-vol atile. they define the size of the area to be software protected against write instructions. srwd bit: the status register write disable (srwd) bit is operated in conjunction with the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits. instructions each instruction starts with a single-byte code, as summarized in the following table . if an invalid instruction is sent (one not contained in the following table), the device automatically deselects its elf. instruction set instruction description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 rej03c0396-0100 rev.1.00 nov.24.2009 page 9 of 20
r1ex25008axx00i/r1ex25016axx00i write enable (wren): the write enable latch (wel) bit must be set prior to each write and wrsr inst ruction. the only way to do this is to send a write enable instruction to the device. as shown in the following figure, to send this instruction to the dev ice, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the de vice then enters a wait state. it waits for the de vice to be deselected, by chip select ( s ) being driven high. write enable (wren) sequence s w c d q instruction 0123456 high-z v ih v il v ih v il v ih v il v ih v il 7 rej03c0396-0100 rev.1.00 nov.24.2009 page 10 of 20
r1ex25008axx00i/r1ex25016axx00i write disable (wrdi): one way of resetting the write enable latch (wel) bit is to send a wr ite disable instruction to the device. as shown in the following figure, to send this instruction to the device, ch ip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits fo r the device to be desel ected, by chip select ( s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the follo wing events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion write disable (wrdi) sequence s w c d q instruction 1 0 234567 high-z v ih v il v ih v il v ih v il v ih v il rej03c0396-0100 rev.1.00 nov.24.2009 page 11 of 20
r1ex25008axx00i/r1ex25016axx00i read status register (rdsr): the read status register (rdsr) instructi on allows the status register to be read . the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device . it is also possible to read the status register continuously, as shown in the following figure. read status register (rdsr) sequence s w c d q status register out 01234567 0 1 2 3 4 5 6 77 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il the status and control bits of th e status register are as follows: wip bit: the write in progress (wip) bit indicates whether the memory i s busy with a write or write status register cycle. when set to 1, such a cycle is in progress. when reset to 0, no such cycles are in progress. wel bit: the write enable latch (wel) bit indicates the status o f the internal write enable latch. when set to 1, the internal write enable latch is set. when set to 0, the internal wr ite enable latch is reset and no write or write status register instructions are accepted. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-vol atile. they define the size of the area to be software protected against write instructions. these bits are written wi th the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits are set to 1, the relevant memory area (as defined in t he status register format table) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. srwd bit: the status register write disable (srwd) bit is operated in conjunction with the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal allows the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and wri te protect ( w ) signal is driven low). in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. rej03c0396-0100 rev.1.00 nov.24.2009 page 12 of 20
r1ex25008axx00i/r1ex25016axx00i write status register (wrsr): the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruc tion must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the instruction sequence is shown in the following figure. the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 a nd b0 of the status register. b6, b5 and b4 are always read as 0. chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed write status regist er cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value o f the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cyc le, and is 0 when it is completed. when the cycle is completed, write enable latch (wel) is reset. the write st atus register (wrsr) instruction allows the user to change the values of the block protect (bp1, bp0) bits, to de fine the size of the area that is to be treated as read-only, as defined in the status register format table. the write status register (wrsr) instruction also allows th e user to set or reset the status register write disable (srwd) bit in accordance w ith the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal allows the device to be put in the hardware protected mode (hpm). the write st atus register (wrsr) instruction is not executed once the hard ware protected mode (hpm) is entered. the contents of the status register wr ite disable (srwd) and block protect (bp1 , bp0) bits are frozen at their current values just before the start of the execution of the write status register (wrsr) in struction. the new, updated values take effect at the moment of completion of the execution of write status register (wrs r) instruction. write status register (wrsr) sequence s w c d q status register in msb 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il rej03c0396-0100 rev.1.00 nov.24.2009 page 13 of 20
r1ex25008axx00i/r1ex25016axx00i read from memory array (read): as shown in the following figure, to send this instruction to the d evice, chip select ( s ) is first driven low. the bits of the instruction byte and the address bytes are then shifted in, on serial data input (d). the a ddresses are loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select ( s ) continues to be driven low, the internal address register is auto matically incremented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter ro lls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the addressed first byte can be any byte within any page. th e instruction is not accepted, and is not executed, if a write cycle is currently in progress. read from memory array (read) sequence s w c d q 16-bit address data out 2 data out 1 01234567 a0 a1 a2 a3 a13 a14 a15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 0 1 2 3 4 5 6 77 instruction note: 1. depending on the memory size, as shown in the fo llowing table, the most signi ficant address bits are don?t care. address range bits device r1ex25016a r1ex25008a address bits a10 to a0 a9 to a0 notes: 1. b15-b11 are don?t care on the r1ex25016a 2. b15-b10 are don?t care on the r1ex25008a rej03c0396-0100 rev.1.00 nov.24.2009 page 14 of 20
r1ex25008axx00i/r1ex25016axx00i write to memory array (write): as shown in the following figure, to send this instruction to the d evice, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on seria l data input (d). the instruction is terminated by driving chip select ( s ) high at a byte boundary of the input data. in the case of the following figure, this occurs after the eighth bit of the data byte h as been latched in, indicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a peri od t wc (as specified in ac characteristics). at the end of the cycle, the write in progress (wip) bit i s reset to 0. if, though, chip select ( s ) continues to be driven low, as shown in the following figure, the next byte of the input data is shifted in, so that more than a single byte, starting from the given address towards the end of t he same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant bits of the interna l address counter are incremented. if the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (the page size of these device is 32 bytes). the instruction is not accepted, and is not executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. byte write (write) sequence (1 byte) s w c d q 16-bit address data byte 1 01234567 0 1 2 3 13 14 15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 0 1 2 3 instruction note: 1. depending on the memory size, as shown in address range bits table, the most significant address bits are don?t care. rej03c0396-0100 rev.1.00 nov.24.2009 page 15 of 20
r1ex25008axx00i/r1ex25016axx00i byte write (write) sequence (page) s w c d q 16-bit address data byte 1 01234567 0 1 2 3 13 14 15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 0 1 2 3 instruction s w c d q data byte 3 data byte n 32 33 34 35 36 37 38 39 7 40 41 42 43 44 45 46 47 high-z v ih v il v ih v il v ih v il 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 data byte 2 note: 1. depending on the memory size, as shown in address range bits table, the most significant address bits are don?t care. rej03c0396-0100 rev.1.00 nov.24.2009 page 16 of 20
r1ex25008axx00i/r1ex25016axx00i data protect the protection features of the device ar e summarized in the following table. wh en the status register write disable (srwd) bit of the status register is 0 (its initial delivery st ate), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction, regardless weather write protect ( w ) is driven high or low. when the status register write disable (srwd) bit of the stat us register is set to 1, two cases need to be considered, depending on the state of write protect ( w ): ? if write protect ( w ) is driven high, it is possible to write to the status register pro vided that the write enable latch (wel) bit has previously been set by a write enable (wren) inst ruction. ? if write protect ( w ) is driven low, it is not possible to write to the status register ev en if the write enable latch (wel) bit has previously been set by a write enable (wren) instructio n. (attempts to write to the status register are rejected, and are not accep ted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: ? by setting the status register write disable (srwd) bit after driving w rite protect ( w ) low. ? by driving write protect ( w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is t o pull write protect ( w ) high. if write protect ( w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp1, bp0) bits of the status register, c an be used. write protected block size status register bits array addresses protected bp1 bp0 protected blocks r1ex25016a r1ex25008a 0 0 none none none 0 1 upper quarter 600h 7ffh 300h 3ffh 1 0 upper half 400h 7ffh 200h 3ffh 1 1 whole memory 000h 7ffh 000h 3ffh protection modes memory protect signal srwd bit mode write protection of the status register protected area * 1 unprotected area * 1 1 0 software protected (spm) status register is writable (if the wren) instruction has set the wel bit). the values in the bp1 and bp0 bits can be changed. write protected ready to accept write instructions 0 0 1 1 0 1 hardware protected (hpm) status register is hardware write protected. the values in the bp1 and bp0 bits cannot be changed. write protected ready to accept write instructions note: 1. as defined by the values in the block protected (bp1, bp0) bits of the status register, as shown in the former table. rej03c0396-0100 rev.1.00 nov.24.2009 page 17 of 20
r1ex25008axx00i/r1ex25016axx00i hold condition the hold ( hold ) signal is used to pause any serial communicati ons with the device wit hout resetting the clocking sequence. during the hold condition, the serial data output (q) is high im pedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device mu st be selected, with chip select ( s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold ( hold ) signal is driven low at the same tim e as serial clock (c) already being low (as shown in the following figure). the hold condition ends when the hold ( hold ) signal is driven high at the same tim e as serial clock (c) already being low. the following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. hold condition activation c hold hold status hold status notes data protection at v cc on/off when v cc is turned on or off, noise on s inputs generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to unintentional program mode. to prevent this unintentional programming, this eeprom have a power on reset function. be careful of the notices described below in order for the power on reset function to operate correctly. ? s should be fixed to v cc during v cc on/off. low to high or high to low transition during v cc on/off may cause the trigger for the unintentional programming. ? v cc should be turned on/off after the eep rom is placed in a standby state. ? v cc should be turned on from the ground level (v ss ) in order for the eeprom not to enter the unintentional programming mode. ? v cc turn on rate should be slower than 2 s/v. ? when wrsr or write instruction is executed before v cc turns off, v cc should be turned off after waiting write cycle time (t w ). rej03c0396-0100 rev.1.00 nov.24.2009 page 18 of 20
r1ex25008axx00i/r1ex25016axx00i package dimensions R1EX25008ASA00I/r1ex25016asa00i (prsp0008df-b / previ ous code: fp-8dbv) prsp0008df-b p-sop8-3.9x4.89-1.27 a l e c b d e a b c x y h z l 2 1 1 e 1 mass[typ.] 0.08g 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0.14 0.254 3.90 0.406 0.60 0.889 1.73 reference symbol dimension in millimeters min nom max previous code jeita package code renesas code fp-8dbv 5.15 1 a p 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p * 3 * 2 * 1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e rej03c0396-0100 rev.1.00 nov.24.2009 page 19 of 20
r1ex25008axx00i/r1ex25016axx00i rej03c0396-0100 rev.1.00 nov.24.2009 page 20 of 20 r1ex25008ata00i/r1ex25016ata00i (ptsp0008jc-b / previous code: ttp-8dav) ptsp0008jc-b p-tssop8-4.4x3-0.65 a l e c b d e a b c x y h z l 2 1 1 e 1 mass[typ.] 0.034g 3.00 1.00 0.13 0 8 6.40 0.10 0.15 0.20 0.25 0.03 0.07 0.10 4.40 0.40 0.50 0.60 1.10 reference symbol dimension in millimeters min nom max previous code jeita package code renesas code ttp-8dav 3.30 1 a p 0.15 0.20 6.60 6.20 0.65 0.10 0.805 * 1 85 e * 2 index mark 14 * 3 p m x y f a d e h z b detail f 1 1 a l l p terminal cross section ( ni/pd/au plating ) c b note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e
revision history r1ex25008axx00i/r1ex25016axx00i data sheet contents of modification rev. date page description 1.00 nov.24.2009 ? initial issue
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